Research Activities
- Multicore & MultiProcessor System-on-Chip (MPSoC) design
- Performance and energy consumption estimation for design space exploration
- Simulation speedup using: Transaction Level Modeling (TLM), application sampling and emulation on FPGA.
- Reconfigurable MPSoC architectures for Automotive Applications
- (Meta-)Heuristics for Design Space Exploration
According to Moore's law, more and more transistors will be integrated on a single chip. Such a huge transistor budget makes it increasingly difficult for engineers to design and verify the very complex chips that result, and in turn widens the gap between silicon capacity and design productivity. MultiProcessor Systems-on-Chip (MPSoC) architecture has thus become a solution for designing embedded systems dedicated to applications that require intensive computations. The most important design challenges in such systems consists in exploring the huge architectural solution space appropriately. In addition, MPSoC are are becoming heterogeneous, and can contain: memories (Cache, SRAM, FIFO...), processors (MCU, DSP, ...), interconnecting elements (Bus, Crossbar, NoC...), I/O peripherals, accelerators (FPGA, ASIP), etc.
An efficient and fast design space exploration (DSE) of such systems needs a set of tools capable:
- Rapid Design Space Exploration (DSE) of processor micro-
architectures to find a "good" micro-architecture configuration
for a specific application or set of applications.
- Rapid Code Space Exploration (CSE) to find
efficient compilation for a given application
executed on a given target micro-architecture.
On the other hand, energy consumption has emerged as a primary design metric when developing MPSoC circuit taking into account silicon integration, IP multiplicity and clock frequency rise.
- Melhem TAWK, Ph.D. student, Fast performance and power evaluation for MPSoC design, November 2005–present
- Jehangir KHAN, PH.D student, Embedded System Design for Automotive Safety, Sept. 2006-present.
- Hajer CHTIOUI, PH.D student, Cache Architectures for MPSoC plateforms, in cooperation with M.abid and J.L.Dekeyser 2007-present.
- Naim HARB, PH.D student, Reconfigurable MPSoC architecture for Automotive Safety Applications, Sept. 2008-present.
- Jamel TAYEB, Ph.D., Performance and energy optimization of VMs on Itanium's EPIC architecture, November 2004-2008. Presently with Intel Corp (Hillsboro, Oregon, USA)
- Rabie BENATITALLAH, Ph.D., Performance/power co-estimation in high level SoC design, INIRIA-FUTURS co-supervised with J.L.Dekeyser and S.Meftali, October 2004-2008. Presently Post-Doct at LAMIH, Univ. of Valenciennes.
- Nicolas INGLART, PH.D. thesis, Fast complier optimization and architecture design space exploration for Intel Itanium and Xscale based embedded systems, September 2004. Passed away in 04/2008
- Hassan SBEYTI, Ph.D., Embedded micro-architecture optimization for multimedia applications, September 2002-December 2005. Presently Professor at Arab Open University at Beirut Libanon.
- Nassima KADRI, Master, Power aware code compression techniques for embedded platforms, co-supervised with Pr A.R.Baba-Ali (EE department Univ of Algiers, Algeria), September 2001- June 2004. Presently Associate Professor at Ecole nationale Supérieure d'Informatique (ESI), Algiers, Algeria.
